Flash memory has been widely used in electronic products. However, limit by the data arrangement and the sequentially accessing feature of the flash memory in prior art, flash memory access performance cannot increased obviously without functions of partial read and partial write provided by flash memory itself. It is a big issue for a high-speed data access requirement.
As known in the art, a page is defined as a basic data access unit of a flash memory and each page is formed by a plurality of data sectors and a plurality of data correction sets. Also, the data sectors and the data correction sets have relation of the one to one correspondence. Size of a page varies with the capacity of the flash memory. For example, size of a 512-page, a low-capacity flash memory, is (512 bytes+16 bytes); wherein 512 bytes indicate the total bytes of all data sectors in one page and 16 bytes indicate the total bytes of all data correction sets in one page. Another example, size of 2K-page, a high-capacity flash memory, is (2K bytes+64 bytes); wherein 2K bytes indicate the total bytes of all data sectors in one page and 64 bytes indicate the total bytes of all data correction sets in one page. A data correction set comprises at least one set of error correction code, e.g. ECC, which is generated in response to a data sector via a well-known data correction algorithm.
FIG. 1 depicts a data arrangement of a flash memory in prior art. Page P1 comprises four data sectors S11˜S14, and four data correction sets E11˜E14 corresponding to the four data sectors S11˜S14, and each data correction set includes one set of error correction code. These four data sectors S11˜S14 and four data correction sets E11˜E14 together form a Page P1. By using 2K-Page as an example, the size of each data sector S11˜S14 is 512 bytes, and the size of each data correction set is 16 bytes. In addition, for increasing the accessing speed of the flash memory, there is usually a data access buffer (not shown in FIG. 1) for storing data temporarily and transferring data rapidly. Detail description of the data access buffer will be omitted, because the data access buffer can be implemented by conventional registers.
Conventionally, as depicted in FIG. 1, the four data sectors S11˜S14 are arranged opposite the four data correction sets E11˜E14, respectively. According to the arrangement of the flash memory in prior art, if a data sector within Page P1 needs to be accessed, a plurality of unnecessary data sectors or data correction sets will be accessed to the data access buffer if the flash memory does not have functions of partial read and partial write. As FIG. 1 depicting, if a microprocessor needs to access data in the data sector S12 in an event, data correction set E12 will be also accessed for detecting errors in the data sector S12. However, for accessing data correction set E12, two data sectors S13, S14, and one data correction set E11 will be also accessed to the data access buffer cause of the conventional data arrangement and sequentially accessing feature of the flash memory. Accessing unnecessary data sectors and data correction sets are wasting time and wasting space of data access buffer. Even the flash memory has functions of partial read and partial write, a pointer, for marking destination of the storing data, will also need to move twice in an event for accessing data sector S12 and its data correction set E12.
Another defect of prior art is, an error coverage rate of a flash memory cannot be increased efficiently because each set of error correction code in the data correction set usually can only detect one bit error in one data sector at a time. Even more complicate data correction algorithms, for error detecting, developed for increasing error coverage rate, the time for processing data is also increasing obviously.
For improving data access performance of the flash memory and increasing the error coverage rate efficiently without much extra processing time, is the purpose of this present invention.